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16 - bit, isolated sigma - delta modulator data sheet ad7402 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibilit y is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pat ent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 10 mhz internal clock rate 16 bits , no missing codes signal - to - noise ratio (snr): 8 7 db typical effec tive number of bits (enob): 13.5 bits typical typical offset drift vs. temperature: 1. 7 v/c on - board digital isolator on - board reference full - scale analog input range: 320 mv ?40c to +1 0 5c operating range high common - mode transient immunity: >25 kv/ s 8 - lead , wide - body soic, with increased cree page package slew rate limited output for low electromagnetic interference (emi) safety and regulatory approvals ul recognition 500 0 v rms for 1 minute per ul 1577 c sa component acceptance notice 5a vde certificate of conformity din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 125 0 v peak applications shunt current monitoring ac motor controls power and solar invert ers wind turbine inver ters data acquisition syste ms analog - to - digital and opto - isolator replacements functional block dia gram figure 1 . general description the ad7402 1 is a high performance, second - order, - modulator that converts an analog input signal into a high speed, single - bit data stream, with on - chip digital isolation based on analog devices, inc., i coupler? technology. the ad7402 operates from a 4. 5 v to 5.5 v (v dd1 ) power supply and accepts a differential input sign al of 250 mv (320 mv full scale). the differential input is ideally suite d to shunt voltage monitoring in high voltage applications where galvanic isolation is required. the analog input is continuously sampled by a high performanc e ana log modulator, and converted to a ones density, digital output stream with a data rate of 1 0 mhz. the o riginal information can be reconstructed wit h an appropriate digital filter to achieve 87 db signal to noise ratio (snr) at 39 ksps. the serial input/output can use a 3 v to 5 .5 v or a 3 .3 v supply (v dd2 ). the serial interface is digitally isolated. high speed complementary m etal oxide semiconductor (cmos) technology , combined with monolithic transformer technology, means the on - chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. the ad7402 device is offered in a n 8 - lead , wide body soic package and has an operating tempe rature range of ?40c to +10 5c. 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. 12898-001 - adc vin+ gnd1 vdd1 vdd2 vin? ad7402 gnd2 clk encoder clk decoder clk decoder dat a encoder clock buf ref mclkout (10mhz) mdat
ad7402 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 package characteristics ............................................................... 5 insulation and safety - related specifications ............................ 5 regulatory information ............................................................... 5 din v vde v 0884 - 10 (vde v 0884- 10):2006 - 12 insulation characteristics .............................................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 ter mi nolo g y .................................................................................... 12 theory of operation ...................................................................... 13 circ uit information .................................................................... 13 analog input ............................................................................... 13 differential inputs ...................................................................... 14 digital output ............................................................................. 14 applications information .............................................................. 15 curr ent sensing applications ................................................... 15 voltage sensing applications .................................................... 15 input filter .................................................................................. 15 digital filter ................................................................................ 16 power supply considerations ................................................... 19 grounding and layout .............................................................. 19 insulation lifetime ..................................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 6/15 rev. 0 to rev. a changes to figure 1 .......................................................................... 1 changes to ordering guide .......................................................... 20 2/1 5 revision 0: initial version
data sheet ad7402 rev. a | page 3 of 20 specifications v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in + = ? 250 mv to + 250 mv , v in ? = 0 v , t a = ?40c to +10 5c, tested with s inc 3 filter, 256 decimation rate, as defined by verilog code, unless otherwise noted. all voltages are relative to their respective ground. table 1. parameter min typ max unit test conditions/comments static performance resolution 16 bits filter output truncated to 16 bits integral nonlinearity (inl) 1 1 5 lsb differential nonlinearity (dnl) 1 0.99 lsb guaranteed no missed codes to 16 bit s offset error 1 0.2 0.75 mv offset drift vs. temperature 1.7 5 v/c offset drift vs. v dd1 85 v/v gain error 1 0.2 0.5 % fsr gain error drift vs. temperature 18 32 ppm/c 11 20 v/c gain error drift vs. v dd1 0.2 mv/v analog input input voltage range ? 320 +320 mv input common - mode voltage range ? 200 to +300 dynamic input current 19 28 a v in + = 250 mv, v in ? = 0 v 0.05 a v in + = 0 v, v in ? = 0 v input capacitance 14 pf dynamic specifications v in + = 35 hz signal - to - (noise + distortion) ratio (sinad) 1 74 82 db signal -to - noise ratio (snr) 1 86 87 db total harmonic distortion (thd) 1 ?8 4 db peak harmonic or spurious noise (sfdr) 1 ?8 4 db effective number of bits (enob) 1 12 13.5 bits noise f ree code resolution 1 14 bits isolation transient immunity 1 25 30 kv/s logic outputs output high voltage, v oh v dd2 ? 0.1 v i o = ?200 a output low voltage, v ol 0.4 v i o = +200 a power requirements v dd1 4.5 5.5 v v dd2 3 5.5 v i dd1 26 31 ma v dd1 = 5.5 v i dd2 6 7 ma v dd2 = 5.5 v 4.5 5.5 ma v dd2 = 3.3 v power dissipation 209 mw v dd1 = v dd2 = 5.5 v 1 see the terminology section .
ad7402 data sheet rev. a | page 4 of 20 timing specifications v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, t a = ?40c to +105c, unless otherwise noted. table 2. parameter 1 min typ max unit description f mclkout 2 9.4 10 10.6 mhz master clock output frequency t 1 3 10 ns data access time after mclkout rising edge t 2 3 44 ns data hold time after mclkout falling edge t 3 33 ns master clock low time t 4 33 ns master clock high time 1 sample tested during initial release to ensure compliance. 2 mark space ratio for clock output is 45/55 to 55/45. 3 defined as the time required for the output to cross 0.8 v or 2.0 v for vdd2 = 3 v to 3.6 v, or when the output crosses 0.8 v or 0.7 vdd2 for vdd2 = 4.5 v to 5.5 v, as outlined in figure 2. measured with a 200 a load and a 25 pf load capacitance. figure 2. data timing 1 see note 3 of table 2 for further details. mdat mclkout 2.0v or 0.7v v dd2 1 2.0v or 0.7v v dd2 1 t 4 t 1 t 2 t 3 0.8v 0.8v 12898-002
data sheet ad7402 rev. a | page 5 of 20 package characterist ics table 3. parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i- o 10 12 capacitance (input to output) 1 c i- o 2.2 pf f = 1 mhz ic junction to ambient thermal resistance ja 105 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 1 the device is considered a 2 - terminal device: pin 1 to pin 4 are shorted together, and pin 5 to pin 8 are shorted together. insulation and safet y - related specificatio ns table 4 . parameter symbol value unit test conditions /comments input - to - output momentary withstand voltage v iso 500 0 min v 1- minute duration minimum external air gap (clearance) l(i01) 8.1 min 1 , 2 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min 1 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.034 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti > 400 v din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table i) 1 in accordance with iec 60950 - 1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes 2000 meters. 2 consideration must be given to pad layou t to ensure the minimum required distance for clearance is main tained. regulatory informati on table 5. ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 2 5000 v rms isolation voltage single protection basic insulation per csa 60950-1- 07 and iec 60950-1, 810 v rms (1145 v peak ) maximum working voltage 3 reinforced insulation per din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12, 1250 v peak reinforced insulation per csa 60950-1- 07 and iec 60950- 1, 405 v rms (583 v peak ) maximum working voltage 3 reinforced insulation per iec 60601 - 1, 250 v rms (353 v peak ) maximum working voltage file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each ad7402 - 8 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 15 a). 2 in accordance with din v vde v 0884 - 10, each ad7402 - 8 is proof tested by appl ying an insulation test voltage 2344 v peak for 1 second (partial discharge detection limit = 5 pc). 3 rating is calculated for a pollution degree of 2 and a material group iii. the ad7402 ri - 8 - 1 package materia l is rated by csa to a cti of > 400 v and therefore material group ii.
ad7402 data sheet rev. a | page 6 of 20 din v vde v 0884 -10 (vde v 0884 - 10):2006- 12 insulation charac teristics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety da ta is ensured by means of protective circuits. table 6 . description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 300 v rms i to iv for rated mains voltage 450 v rms i to iv for rated mains voltage 600 v rms i to iv for rated mains voltage 1000v rms i to iv climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 1250 v peak input to output test voltage, method b1 v pd(m) 2344 v peak v iorm 1.875 = v pr , 100% production test, t m = 1 second , partial discharge < 5 pc input to - output test voltage, method a v pr(m) after environmental test subgroup 1 2000 v peak v iorm 1.6 = v pr , t m = 60 seconds , partial discharge < 5 pc after input and/or safety test subgroup 2/ safety test subgroup 3 1500 v peak v iorm 1.2 = v pr , t m = 60 seconds , partial discharge < 5 pc highest allowable overvoltage (transient overvoltage, t tr = 10 seconds ) v iotm 8000 v peak surge isolation voltage 1.2 s rise tim e, 50 s, 50% fall time v iosm 12000 v peak safety limiting values (maximum value allowed in the event of a failure, see figure 3) case temperature t s 150 c side 1 (p vdd1 ) and side 2 (p vdd2 ) power dissipation p so 1.19 w insulation resistance at t s , v io = 500 v r io >10 9 figure 3 . thermal derat ing curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 12898-003 safe operating power (w) ambient temperature (c) 0 1 2 0 50 100 150 200
data sheet ad7402 rev. a | page 7 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 7. parameter rating vdd1 to gnd1 ?0.3 v to +6.5 v vdd2 to gnd2 ?0.3 v to +6.5 v analog input voltage to gnd1 ? 1 v to v dd1 + 0.3 v output voltage to gnd2 ?0.3 v to v dd2 + 0.3 v input current to any pin except supplie s 1 10 ma operating temperature range ?40c to +10 5c storage temperature range ?65c to +150c junction temperature 150c pb - free temperature, soldering reflow 260c esd 2 kv ficdm 2 1250 v hbm 3 4000 v 1 transient currents of up to 100 ma do not cause silicon controlled rectifier ( scr ) to latch up. 2 jesd22 - c101; rc network: 1 , package capacitance ( c pkg ) ; class: iv. 3 esda/jedec js - 001- 2011; rc network: 1.5 k, 100 pf; class: 3a. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any o ther conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 8 . maximum continuous working voltage 1 parameter max unit constraint ac voltage bipolar waveform 1250 v peak 20 - year minimum lifetime (vde approved working voltage) unipolar waveform 1250 v peak 20- year minimum lifetime dc voltage 1250 v peak 20- year minimum lifetime 1 refers to continuous voltage magnitude imp osed across the isolation barrier. esd caution
ad7402 data sheet rev. a | page 8 of 20 pin configuration an d function descripti ons figure 4 . pin configuration table 9 . pin function descriptions pin no. mnemonic description 1 vdd1 supply voltage, 4.5 v to 5.5 v. this is the supply voltage for the isolated side of the ad7402 and is rela tive to gnd1. 2 vin+ positive analog input. 3 vin? negative analog input. normally connected to gnd1. 4 gnd1 ground 1. this is the ground reference point for all circuitry on the isolated side. 5 gnd2 ground 2. this is the ground reference point for all circuitry on the nonisolated side. 6 mdat serial data output. the single bit modulator output is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the mclkout input and are valid on the following mclkout falling edge . 7 mclkout master clock logic output, 10 mhz ( typical). the bit stream from the modulator is valid on the falling edge of mclkout. 8 vdd2 supply voltage, 3 v to 5.5 v. this is the supply voltage for the nonisolated side and is relative to gnd2. 12898-004 vdd1 vdd2 mclkout mdat gnd2 vin+ vin? gnd1 1 2 3 4 8 7 6 5 ad7402-8 top view (not to scale)
data sheet ad7402 rev. a | page 9 of 20 typical performance characteristics t a = 25c, v dd1 = 5 v, vdd2 = 5 v, using s inc3 filter with a 256 oversampling ratio ( osr ) , unless otherwise noted. figure 5 . psrr vs. supply ripple frequency figure 6 . cmrr vs. common - mode ripple frequency figure 7 . sinad vs. analog input frequency figure 8 . fast fourier transform (fft) figure 9 . typical dnl error figure 10 . typical inl error 12898-005 psrr (db) supply ripple frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 200mv p-p sine wave on vdd1 1nf decoupling 10k 100k 1m 12898-006 cmrr (db) common-mode ripple frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10k 100k 1m sinc3 osr = 256 filter unfiltered 12898-007 sinad (db) analog input frequency (hz) 0 10 20 30 40 50 60 70 80 90 5.5v 5v 4.5v 10 100 1k 12898-008 magnitude (db) frequency (khz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 f in = 35.8hz snr = 87.4db sinad = 86db thd = ?92db 12898-009 dnl error (lsb) code (k) 0 10 20 30 40 50 60 70 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 12898-010 inl error (lsb) code (k) 0 10 20 30 40 50 60 70 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5
ad7402 data sheet rev. a | page 10 of 20 figure 11 . histogram of codes at code center figure 12 . snr and sinad vs. temperature figure 13 . thd and sfdr vs. temperature figure 14 . offset vs. temperature figure 15 . gain error vs. temperature figure 16 . i dd1 vs. v dd1 at various temperatures 12898-0 1 1 hits per code (k) code 0 100 200 300 400 500 600 700 800 32766 32767 32768 32769 32770 vin+ = vin? = 0v 1m samples 676225 1401 1902 159024 161448 12898-012 snr and sinad (db) temperature (c) 60 70 80 90 100 ?40 ?10 ?25 5 20 50 35 80 65 95 snr sinad f in = 35hz 12898-013 thd and sfdr (db) temperature (c) ?120 ?110 ?100 ?90 ?80 ?70 ?60 thd sfdr f in = 35hz ?40 ?25 ?10 5 20 35 50 65 80 95 12898-014 offset (mv) temperature (c) ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 v dd1 = 5.5v, v dd2 = 5.5v v dd1 = 5.5v, v dd2 = 5.0v v dd1 = 4.5v, v dd2 = 5.5v v dd1 = 4.5v, v dd2 = 3.0v v dd1 = 5.0v, v dd2 = 5.0v v dd1 = 5.0v, v dd2 = 3.3v ?40 ?25 ?10 5 20 35 50 65 80 95 12898-015 gain error (mv) temperature (c) v dd1 = 5.5v, v dd2 = 5.5v v dd1 = 5.5v, v dd2 = 5.0v v dd1 = 4.5v, v dd2 = 5.5v v dd1 = 4.5v, v dd2 = 3.0v v dd1 = 5.0v, v dd2 = 5.0v v dd1 = 5.0v, v dd2 = 3.3v ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?40 ?25 ?10 5 20 35 50 65 80 95 12898-016 i dd1 (ma) v dd1 (v) 0 5 10 15 20 25 30 35 4.50 4.75 5.00 5.25 5.50 t a = ?40c t a = +25c t a = +105c
data sheet ad7402 rev. a | page 11 of 20 figure 17 . i dd1 vs. vin+ dc input at various temperatures figure 18 . i dd2 vs. v dd2 at various temperatures figure 19 . i dd2 vs. vin+ dc input at various temperatures figure 20 . iin+ vs. vin+ dc input figure 21 . clock frequency vs. temperature for various supply voltages 12898-017 i dd1 (ma) vin+ dc input (mv) 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 27.0 ?250 ?125 0 125 250 t a = ?40c t a = +85c t a = +25c t a = +105c 12898-018 i dd2 (ma) v dd2 (v) 0 1 2 3 4 5 6 7 8 9 10 3.0 3.5 4.0 4.5 5.0 5.5 t a = ?40c t a = +25c t a = +105c 12898-019 i dd2 (ma) vin+ dc input (mv) 4 5 6 ?250 ?125 0 125 250 t a = ?40c t a = +25c t a = +85c t a = +105c 12898-020 iin+ (a) vin+ dc input (mv) ?30 ?20 ?10 0 10 20 30 ?320 ?240 ?160 ?80 0 80 160 240 320 12898-021 clock frequency (mhz) temperature (c) 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 v dd1 = 4.5v v dd1 = 5.0v v dd1 = 5.5v ?40 ?25 ?10 5 20 35 50 65 80 95
ad7402 data sheet rev. a | page 12 of 20 terminology differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are specified negative full scale, ?250 mv (v in+ ? v in? ), code 7168 for the 16 - bit lev el, and specified positive full scale, +250 mv (v in+ ? v in? ), code 58,368 for the 16 - bit level. offset error offset error is the deviation of the midscale code (32,768 for the 16- bit level) from the ideal v in+ ? v in? (that is, 0 v). gain error the gain er ror includes both positive full - scale gain error and negative full - scale gain error. positive full - scale gain error is the deviation of the specified positive full - scale code (58,368 for the 16- bit level) from the ideal v in+ ? v in? (250 mv) after the offse t error is adjusted out. negative full - scale gain error is the deviation of the specified negative full - scale code (7168 for the 16- bit level) from the ideal v in+ ? v in? (?250 mv) after the offset error is adjusted out. signal -to - noise - and - distortion ratio (sinad) sinad is the measured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), including harmon ics, but excluding dc. signal -to - noise ratio (snr) snr is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. the theoretical signal - to - noise ratio for an ideal n - bit converter with a si ne wave input is given by signal - to - noise ratio = ( 6.02 n + 1.76 ) db therefore, for a 12 - bit converter, the snr is 74 db. isolation transient immunity the isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. the ad7402 was tested using a transient pulse frequency of 100 khz. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7402 , it is defined as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 (db) + + + + = v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. effective number of bits (enob) enob is defined by enob = ( sinad ? 1.76)/6.02 bits noise free code resolution noise free code resolution represents the resolution in bits for whic h there is no code flicker. the noise free code resolution for an n - bit converter is defined as noise free code resolution (bits) = log 2 (2 n /peak - to - peak noise) the peak - to - peak noise in lsbs is measured with v in+ = v in? = 0 v. common - mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at 250 mv frequency, f, to the power of a +250 mv peak - to - peak sine wave applied to the common - mode voltage of v in+ and v in? of frequency, f s , as cmrr (db) = 10 log( pf/pf s ) where: pf is th e power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but not the linearity of the converter. psrr is the maximum ch ange in the specified full - scale (250 mv) transition point due to a change in power supply voltage from the nominal value.
data sheet ad7402 rev. a | page 13 of 20 theory of operation circuit information the ad7402 i solated - modulator converts an analog input signal into a high speed ( 10 mhz maximum ), single - bit data stream; the time average single - bit data from the modulator is directly proportional to the input signal. figure 22 shows a typical application circuit where the ad7402 is used to provide isolation between the analog input, a current sensing resistor or shunt, and the digital output, which is then processed by a digital filter to provide an n - bit word. analog input the differential analog input of the ad7402 is implemented with a switched capacitor circuit. this circuit implements a second - order modulator stage that digitizes the input signal into a single - bit output stream. the sample clock (mclkout ) provides the clock signal for the conversion process as well as the output data framing clock. this clock source is internal on the ad7402 . the analog input signal is continuously sampled by the modulator and compared to an in ternal voltage reference. a digital stream that accurately represents the analog input over time appears at the output of the converter (see figure 23). a differentia l signal of 0 v ideally results in a stream of alter - nating 1s and 0s at the mdat output pin. this output is high 50% of the time and low 50% of the time. a differential input of 250 mv produces a stream of 1s and 0s that are high 89.06% of the time . a dif ferential input of ?250 mv produces a stream of 1s and 0s that are high 10.94% of the time. a differential input of 320 mv ideally results in a stream of all 1s. a differential input of ? 320 mv ideally results in a stream of all 0s. the absolute full - scale range is 320 mv and the specified full - scale performance range is 250 mv, as shown in tabl e 10. table 10 . analog input range analog input voltage input (mv) positive full - scale value +320 positive specified performance input +250 zero 0 negative specified performance input ?250 negative full - scale value ?320 figure 22 . typical application circuit figure 23 . an alog input vs. modulator output 12898-022 - mod/ encoder nonisol a ted 5v/3.3v vdd1 vdd2 vin+ vin? gnd1 gnd2 gnd mda t mda t sinc3 fi l ter* ad7402 mclkout sda t cs sclk mclk 100nf +400v ?400v 220pf 220pf 10? 5.1v r shunt 10? decoder 1nf 10f ga ted drive circuit flo a ting power supp l y ga ted drive circuit flo a ting power supp l y mo t or *this fi l ter is implemented with an fpg a or ds p vdd modul a t or output +fs analog input ?fs analog input analog input 12898-023
ad7402 data sheet rev. a | page 14 of 20 to reconstruct the original information, this output must be digitally filtered and decimated. a sinc3 filter is recommended b ecause it is one order higher than that of the ad7402 modulator , which is a second - order modulator. if a 256 decimation rate is used, the resulting 16 - bit word rate is 39 ksps . see the digital filter section for more detailed information on the sinc filter implementation. figure 24 shows the transfer function of the ad7402 relative to the 16 - bit output. figure 24 . filtered and decimated 16 - bit transfer function differential inputs the analog input to the modulator is a switched capacitor design. the analog signal is converted into charge by highly linear sampling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 25 . a signal source driving the analog input must provide the charge onto the sampl ing capacitors every half mclkout cycle and settle to the required accuracy withi n the next half cycle. figure 25 . analog input equivalent circuit because the ad7402 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common - mode noise at each input. digital output the ad7402 mdat output driver is a slew rate limited driver. this driver lowers electromagnetic emi ssions, thus minimizing electromagnetic interference , both conducted and radiated. 65535 58368 specified range analog input adc code 7168 ?320mv ?250mv +250mv +320mv 0 12898-024 a b 300? vin? a b b b 300? vin+ 1.9pf 1.9pf a a mclkin 12898-025
data sheet ad7402 rev. a | page 15 of 20 applications information current sensing applications the ad7402 is ideally suited for current sensing applications where the voltage across a shunt resistor (r shunt ) is monitored. the load current flowing through an external shunt resistor produces a voltage at the input terminals of the ad7402 . the ad7402 provides isolation between the analog input from the current sensing resistor and the digital outputs. by selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. choosing r shunt the shunt resistor (r shunt ) values used in conjunction with the ad7402 are determined by the specific application requirements in terms of voltage, current, and power. small resistors minimize power dissipation, whereas low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. the final values chosen are a compromise between low power dissipation and accuracy. higher value resistors use the full performance input range of the adc, thus achieving maximum snr performance. low value resistors dissipate less power but do not use the full performance input range. the ad7402 , however, delivers excellent performance, even with lower input signal levels, allowing low value shunt resistors to be used while maintaining system performance. to choose a suitable shunt resistor, first determine the current through the shunt. the shunt current for a 3-phase induction motor can be expressed as i rms = pfefv p w ??? 73.1 where: i rms is the motor phase current (a rms) p w is the motor power (watts) v is the motor supply voltage (v ac) ef is the motor efficiency (%) pf is the power efficiency (%) to determine the shunt peak sense current, i sense , consider the motor phase current and any overload that may be possible in the system. when the peak sense current is known, divide the voltage range of the ad7402 (250 mv) by the peak sense current to yield a maximum shunt value. if the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced and less of the adc input range can be used. figure 26 shows the sinad performance characteristics and the enob of resolution for the ad7402 for different input signal amplitudes. figure 27 shows the rms noise performance for dc input signal amplitudes. the ad7402 performance at lower input signal ranges allows smaller shunt values to be used while still maintaining a high level of performance and overall system efficiency. figure 26. sinad vs. v in+ ac input signal amplitude figure 27. rms noise vs. v in+ dc input signal amplitude r shunt must be able to dissipate the i2r power losses. if the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. this open circuit can result in a differential voltage across the terminals of the ad7402 , in excess of the absolute maximum ratings. if i sense has a large high frequency component, choose a resistor with low inductance. voltage sensing applications the ad7402 can also be used for isolated voltage monitoring. for example, in motor control applications, it can be used to sense the bus voltage. in applications where the voltage being monitored exceeds the specified analog input range of the ad7402 , a voltage divider network can be used to reduce the voltage being monitored to the required range. input filter in a typical use case for directly measuring the voltage across a shunt resistor, the ad7402 can be connected directly across the shunt resistor with a simple rc low-pass filter on each input. 12898-026 sinad (db) vin+ ac input signal amplitude (mv) 60 65 70 75 80 85 90 0 50 100 150 200 250 14-bit enob 13-bit enob 11-bit enob f in = 35hz v dd1 = 5v v dd2 = 5v t a = 25c 12-bit enob 12898-027 rms noise (lsb) rms noise (lsb) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ?250 ?170 ?90 ?10 70 150 230 dc input 100k samples per data point
ad7402 data sheet rev. a | page 16 of 20 the recommended circuit configuration for driving the differential inputs to achieve best performance is shown in figure 28. an rc low - pass filter is placed on both the analog input pins. recommended values for the resistors and capacitors are 10 ? and 220 pf, respectively. if possible, e qualize the source impedance on each analog input to minimize offset. figure 28 . rc low - pass filter input network the input filter configuration for the ad7402 is not li mited to the low - pass structure shown in figure 28 . the differential rc filter configuration shown in figure 29 also achieves excellent performance. reco mmended values for the resistors and capacitor are 22 ? and 47 pf, respectively. figure 29 . differential rc filter network figure 30 compare s the typical performance for the input filter structures outlined in figure 28 and figure 29 for different resistor and capacitor values. figure 30 . snr vs. decimation rate for different filter structures for different resistor and capacitor values digital filter the output of the ad7402 is a continuous digital bit stream. to reconstruct the original input signal information, this output bit stream needs to be digitally filtered and decimated. a sinc filter is recommended due to its simplicity. a sinc3 filter is recommended because it is one order higher than that of the ad7402 modulator, which is a second - order modulator . the type of filter selected, the decimation r ate, and the modulator clock used determines the overall system resolution and throughput rate . the higher the decimation rate, the greater the system accuracy, as illustr ated in figure 31 . however, there is a trade - off between accuracy and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. figure 31 . snr vs. decimation rate for diff erent sincx filter orders a sinc3 filter is recommended for use with the ad7402 . this filter can be implemented on a field programmable gate array (fpga) or a digital signal processor (dsp). equation 1 describes the transfer function of a sinc filter. ( ) ( ) n dr z z dr z h ? ? ? ? ? ? ? ? ? ? = ? ? 1 1 1 1 ) ( (1) where dr is the decimation rate and n is the sinc filter order. the throughput rate of the sinc filter is determined by the modulator clock and the decimation rate selected. dr mclk throughput = mclk is the modulator clock frequency as the decimation rate increases, the data output size from the sinc filte r increases. the output data size is expressed in equation 3. the 16 most significant bits are used to return a 16- bit result. data size = n log 2 dr (3) for a sinc 3 filter, the ?3 db filter response point can be derived from the filter transfer functio n, equation 1, and is 0.262 times the throughput rate. the filter characteristics for a third - order sinc filter are summarized in table 11. table 11 . sinc3 filter c haracteristics for 10 mhz decimation ratio (dr) throughput rate (khz) output data size (bits) filter response (khz) 32 312.5 15 81.8 64 156.2 18 40.9 128 78.1 21 20.4 256 39.1 24 10.2 512 19.55 27 5.1 r vin? r vin+ c c ad7402 12898-028 r v in? r v in+ c ad7402 12898-029 12898-030 snr (db) decimation rate 45 50 55 60 65 70 75 80 85 90 95 10 100 f in = 35hz s) ',))(5(17,$/ s) ',))(5(17,$/ q) 12898-031 snr (db) decimation rate 0 10 20 30 40 50 60 70 80 90 100 10 100 f in = 35hz sinc1 sinc2 sinc3 sinc4
data sheet ad7402 rev. a | page 17 of 20 the following verilog code provides an example of a sinc3 filter implementation on a xilinx? spartan ? - 6 fpga. note that the data is read on the negative c lock edge . it is recommended to read in the data on the negative clock edge. the code is configurable to accommodate decimat ion rates from 32 to 4096. module dec256sinc24b ( input mclk1, /* used to clk filter */ input reset, /* used to reset filter */ input mdata1, /* input data to be filtered */ output reg [15:0] data, /* filtered output */ output reg data_en, input [15:0] dec_rate ); /* data is read on negative clk edge */ reg [36:0] ip_data1; reg [36:0] acc1; reg [36:0] acc2; reg [36:0] acc3; reg [36:0] acc3_d2; reg [36:0] diff1; reg [36:0] diff2; reg [36:0] diff3; reg [36:0] diff1_d; reg [36:0] diff2_d; reg [15:0] word_count; reg word_clk; reg enable; /*perform the sinc action*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 37'd0; /* change 0 to a -1 for twos complement */ else ip_data1 <= 37'd1; /*accumulator (integrator) perform the accumulation (iir) at the speed of the modulator. z = one sample delay mclkout = modulators conversion bit rate */ figure 32 . accumulator always @ (negedge mclk1, posedge reset) begin if (reset) begin /* initialize acc registers on reset */ acc1 <= 37'd0; acc2 <= 37'd0; acc3 <= 37'd0; end else begin /*perform accumulation process */ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end end /*decimation stage (mclkout/word_clk) */ always @ (negedge mclk1, posedge reset) begin if (reset) word_count <= 16'd0; else begin if ( word_count == dec_rate - 1 ) word_count <= 16'd0; else word_count <= word_count + 16'b1; end end always @ ( negedge mclk1, posedge reset ) begin if ( reset ) word_clk <= 1'b0; else begin if ( word_count == dec_rate/2 - 1 ) word_clk <= 1'b1; else if ( word_count == dec_rate - 1 ) word_clk <= 1'b0; end end /*differentiator (including decimation stage) perform the differentiation stage (fir) at a lower speed. z = one sample delay word_clk = output word rate */ figure 33 . differentiator always @ (negedge word_clk, posedge reset) begin if(reset) begin acc3_d2 <= 37'd0; diff1_d <= 37'd0; diff2_d <= 37'd0; mclkin ip_d at a1 acc1+ acc2+ acc3+ + z + z + z 12898-032 wo r d_clk ac c3 di f f1 di f f3 + ? + ? di f f2 z ?1 ? + ? z ?1 z ?1 12898-033
ad7402 data sheet rev. a | page 18 of 20 diff1 <= 37'd0; diff2 <= 37'd0; diff3 <= 37'd0; end else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end end /* clock the sinc output into an output register word_clk = output word rate */ figure 34 . clocking sinc3 output into an output register always @ (negedge word_clk ) begin case ( dec_rate ) 16'd32:begin data <= (diff3[15:0] == 16'h8000) ? 16'hffff : {diff3[14:0], 1'b0}; end 16'd64:begin data <= (diff3[18:2] == 17'h10000) ? 16'hffff : diff3[17:2]; end 16'd128:begin data <= (diff3[21:5] == 17'h10000) ? 16'hffff : diff3[20:5]; end 16'd256:begin data <= (diff3[24:8] == 17'h10000) ? 16'hffff : diff3[23:8]; end 16'd512:begin data <= (diff3[27:11] == 17'h10000) ? 16'hffff : diff3[26:11]; end 16'd1024:begin data <= (diff3[30:14] == 17'h10000) ? 16'hffff : diff3[29:14]; end 16'd2048:begin data <= (diff3[33:17] == 17'h10000) ? 16'hffff : diff3[32:17]; end 16'd4096:begin data <= (diff3[36:20] == 17'h10000) ? 16'hffff : diff3[35:20]; end default:begin data <= (diff3[24:8] == 17'h10000) ? 16'hffff : diff3[23:8]; end endcase end /* synchronize data output*/ always@ (negedge mclk1, posedge reset ) begin if ( reset ) begin data_en <= 1'b0; enable <= 1'b1; end else begin if ( (word_count == dec_rate/2 - 1) && enable ) begin data_en <= 1'b1; enable <= 1'b0; end else if ( (word_count == dec_rate - 1) && ~enable ) begin data_en <= 1'b0; enable <= 1'b1; end else data_en <= 1'b0; end end endmodule word_clk dat a diff3 12898-034
data sheet ad7402 rev. a | page 19 of 20 power supply considerations the ad7402 requires a 5 v vdd1 supply, and there are various means of achieving this. one method is to use an isolated dc-to- dc converter such as the adum6000 . this method provides a 5 v regulated dc supply across the isolation barrier. note that the inherent isolation of the adum6000 is lower than the ad7402 . figure 35. adum6000 isolated 5 v dc-to-dc regulator example another method is to regulate a dc supply on the high voltage side of the isolation barrier using a step-down dc-to-dc regulator, such as the adp2441. figure 36. adp2441 step-down dc-to-dc regulator example grounding and layout it is recommended to decouple the v dd1 supply with a 10 f capacitor in parallel with a 1 nf capacitor to gnd 1 . decouple the v dd2 supply with a 100 nf value to gnd 2 . in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout so that any coupling that occurs equally affects all pins on a given component side. failure to ensure equal coupling can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. place any decoupling used as close to the supply pins as possible. minimize series resistance in the analog inputs to avoid any distortion effects, especially at high temperatures. if possible, equalize the source impedance on each analog input to minimize offset. check for mismatch and thermocouple effects on the analog input printed circuit board (pcb) tracks to reduce offset drift. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ad7402. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 8 summarize the peak voltage for 20 years of service life for a bipolar, ac operating condition and the maximum vde approved working voltages. these tests subjected the ad7402 to continuous cross isolation voltages. to accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. the time to failure values of these units were recorded and used to calculate the acceleration factors. these factors were then used to calculate the time to failure under the normal operating conditions. the values shown in table 8 are the lesser of the following two values: ? the value that ensures at least a 20-year lifetime of continuous use. ? the maximum vde approved working voltage. note that the lifetime of the ad7402 varies according to the waveform type imposed across the isolation barrier. the i coupler insulation structure is stressed differently, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 37, figure 38, and figure 39 illustrate the different isolation voltage waveforms. figure 37. bipolar ac waveform, 50 hz or 60 hz figure 38. unipolar ac waveform, 50 hz or 60 hz figure 39. dc waveform 1289 8-035 5v digital isolation barrier adum6000 ad7402 vdd1 vdd2 5v iso dc-to-dc converter 12898-036 ad7402 vdd2 vdd1 5v digital 5v 4.5v to 36v adp2441 dc-to-dc switching regulator isolation barrier 0v rated peak voltage 12898-037 0v rated peak voltage 12898-038 0v rated peak voltage 12898-039
ad7402 data sheet rev. a | page 20 of 20 outline dimensions figure 40 . 8 - lead standard small outlin e package, with increased creepage [soic_ic] wide body (ri - 8 - 1 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7402 - 8 briz ?40c to +105c 8 - lead standard small outline pa ckage, with increased creepage [soic_ic] ri - 8 - 1 ad7402 - 8briz -rl ?40c to +105c 8- lead standard small outline package, w ith increased creepage [soic_ic] ri -8-1 ad7402 - 8briz - rl7 ?40c to +105c 8- lead standard small outline package, w ith increased creepage [soic_ic] ri -8-1 eval - ad7402 - 8fmcz evaluation board 1 z = rohs compliant part. 09-17-2014-b 8 5 4 1 se a ting plane coplanarit y 0.10 1.27 bsc 1.04 bsc 6.05 5.85 5.65 7.60 7.50 7.40 2.65 2.50 2.35 0.75 0.58 0.40 0.30 0.20 0.10 2.45 2.35 2.25 10.51 10.31 10. 1 1 0.51 0.41 0.31 pin 1 mark 8 0 0.33 0.27 0.20 0.75 0.50 0.25 45 ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12898 - 0- 6/15(a)

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